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? e94x27c1y-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 c) supply voltage v cc 7v operating temperature topr 20 to +75 c storage temperature tstg 65 to +150 c allowable power dissipation p d 960 mw operating conditions supply voltage v cc 50.5 v operating temperature topr 20 to +75 c description the cxa1875ap/am is developed as a 8-bit 5 ch d/a converter compatible with i 2 c bus. features serial control through i 2 c bus 5 channels of 8-bit d/a converter 4 built-in general purpose i/o ports (digital i/o) i/o can be specified to respective ports independently selection of 8 slave addresses possible through address select pins (3 pins) applications i 2 c bus can control ics that do not correspond to i 2 c bus by connecting the dc control pins of them. structure bipolar silicon monolithic ic 8-bit d/a converter compatible with i 2 c bus cxa1875ap/am 16 pin dip (plastic) 16 pin sop (plastic)
2 cxa1875ap/am pin configuration (top view) block diagram 16 15 14 13 12 9 10 11 345678 2 1 sw1 sw0 dac4 dac3 dac2 dac1 dac0 gnd v cc scl sda sad2 sad1 sad0 sw3 sw2 i 2 c bus slave address select pin sw i/o sw i/o dac output sad2 sad1 sad0 latch dac amp dac4 latch dac amp dac3 latch dac amp dac2 latch dac amp dac1 latch dac amp dac0 v cc power on reset level conv- ersion i 2 c bus sda scl level conversion latch level conversion sw0-3 open collector i 2 c decoder v cc reg gnd
3 cxa1875ap/am pin description electrical characteristics (ta=25 c, v cc =5 v) d/a converter block no. item symbol test test contents min. typ. max. unit circuit 6 9 12 ma 1 circuit current i cc 1 dac 0 to 4=127 1 0 +1 lsb 0.1 0.4 0.7 v 4.3 4.6 4.9 v 1+1ma 036 ? 2 3 4 5 6 differential linearity minimum output voltage maximum output voltage output current output impedance dle vmin vmax iout z 0 1 1 1 2 2 v(dac0 to 4=n+1) v(dac0 to 4=n) 128 1 v(dac0 to 4=191) v(dac0 to 4=63) n=0 to 127 dac 0 to 4=0 dac 0 to 4=255 current that can be flowed from pins 3 to 7 dac 0 to 4=127, v( 1 ma) v(1 ma) 2 ma no. symbol equivalent circuit description i/o pin for general purpose i/o port v il max: 1.5 v v ih min: 3 v v ol max: 0.4 v sda i/o pin for i 2 c bus d/a converter output pin gnd pin slave address input pin input at positive logic v il max: 1.5 v v ih min: 3 v power supply pin v cc 150 4.5k v cc 56 v cc 20k 20k 22k v cc 150 4.5k v cc 1 2 9 10 14 15 3 4 5 6 7 8 11 12 13 16 sw1 sw0 sw2 sw3 sda scl dac4 dac3 dac2 dac1 dac0 gnd sad0 sad1 sad2 v cc
4 cxa1875ap/am sw, sad pins no. item symbol min. typ. max. unit 3.0 5.0 v 0 1.5 v 10 a 10 a 0 0.4 v 3 ma 10 pf 0 100 khz 4.7 s 4.0 s 4.7 s 4.0 s 4.7 s 5 s 250 ns 1s 300 ns 4.7 s 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 high level input voltage low level input voltage high level input current low level input current low level output voltage at 3 ma flow to sda (pin 14) maximum flowing current input capacitance maximum clock frequency data change minimum waiting time data transfer start minimum waiting time low level clock pulse width high level clock pulse width minimum start preparation waiting time minimum data hold time minimum data preparation time rise time fall time minimum stop preparation waiting time v ih v il i ih i il v ol i ol c i f scl t buf t hd:sta t low t high t su:sta t hd:dat t su:dat t r t f t su:sto i 2 c bus load conditions: pull up resistance 4 k ? (connected to +5 v) load capacitance 200 pf (connected to gnd) no. item symbol text test contents min. typ. max. unit circuit 1.5 v 3.0 v 10 0 +10 a 10 0 +10 a 0 0.2 0.4 v 7 8 9 10 11 low level input voltage high level input voltage low level input current high level input current low level input voltage v il v ih i il i ih v ol 3 3 3 3 4 st 0 to 3 an input voltage that turns to 0 st 0 to 3 an input voltage that turns to 1 input current when 0.4 v is applied input current when 4.5 v is applied sw 0 to 3=1, output voltage when 1 ma flows in i 2 c bus block items (sda, scl)
5 cxa1875ap/am i 2 c bus control signal electrical characteristics test circuit test circuit 1 test circuit 2 test circuit 3 test circuit 4 t buf scl sda p s t hd:sta t low t r t hd:dat t f t high t su:dat sr t hd:sta t su:sta p t su:sto i 2 c bus a 0.022 +5v 10 5v 100p 100p 100p 100p 100p v 3 4 5 6 7 8 2 1 16 15 14 13 12 9 10 11 i 2 c bus a 0.022 10 100p 3 4 5 6 7 8 2 1 100p 100p 100p 100p v +5v 16 15 14 13 12 9 10 11 1ma i 2 c bus 0.022 10 +5v v 4 16 15 14 13 12 9 10 11 a 3 4 5 6 7 8 2 1 1.5 v (no. 7) 3.0 v (no. 8) 0.4 v (no. 9) 4.5 v (no. 10) v 4 = i 2 c bus 0.022 10 +5v 1ma 3 4 5 6 7 8 2 1 15 14 13 12 9 10 11 16 v
6 cxa1875ap/am definition of i 2 c register with the ic reset all registers are reset to 0 ? : not defined : don t care sub address is auto incremented it can be used as a 6-bit d/a converter by setting the lower two bits of dac 0-4 registors to 0, but take care that the max. voltage of da output will lower about 100 mv compared with the use of 8 bits. control register status register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ref ??? sw3 sw2 sw1 sw0 dac0 (8) dac1 (8) dac2 (8) dac3 (8) dac4 (8) sub address 000 001 010 011 100 101 msb lsb 0 1 0 0 sad2 sad1 sad0 r/w r/w 0: slave receiver 1: slave transmitter sad 0 to 2: 11 to 13 pin 0: "low" 1: "high" bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ponres 0 0 0 st3 st2 st1 st0
7 cxa1875ap/am in brackets ( ) number of bits ref (1): switches d/a converter reference voltage 0:standardizes the inner regulator 1:standardizes voltage resistance divided from v cc sw0 to 3 (1): selects on/off of pins 1, 2, 9 and 10 (each pin is the open collector output of npn transistor) 0:off 1:on dac0 to 4 (8): digital data input register of d/a converter 0:output voltage turns to minimum 255:output voltage turns to maximum ponres (1): detects power on reset 0:master passes from the bus and is reset to 0 after having read this status 1:set to 1 when power supply is turned on or when there has been a power dip st0 to 3 (1): detects and registers the voltage condition of pins 1, 2, 9 and 10 0:1.5 v and below 1:3.0 v and above note) sw0 to 3 effective during 0 i 2 c bus signal there are 2 signals in i 2 c bus. sda (serial data) and scl (serial clock). sda is double-way. as sda is double-way it has 3 state outputs, h, l and hiz. i 2 c transfer begins with start condition and ends with stop condition. l hhizl sda start condition s scl stop condition p
8 cxa1875ap/am i 2 c data write (write from i 2 c controller to ic) i 2 c data read (read from ic to i 2 c controller) read timing ? data read is performed with scl rise. sda scl 1 2 34 5 678 9 1 8 9 msb hiz msb lsb hiz at l during write address ack sub address ack ack data (n) data (n+1) ack 891 89 data (n+2) 89 1 89 ack data data ack p msb hiz lsb hiz 1 hiz hiz s sda scl 1 67891 89 hiz at h during read address ack data ack s 7 p ic output sda scl 1 2 34 5 6 78 9 9 msb lsb data ack ack read timing ? the number of data that can be transferred at a time is confined to units of 8-bit that can be set as required. sub address is incremented automatically.
9 cxa1875ap/am application circuit i 2 c bus 0.022 10 10k 2sc2785 +5v d/a converter output general purpose input port 10k 10k 14 15 13 16 9 10 11 12 general purpose output port 2 3 4 5 6 7 8 1 10k 10k 10k 2sc2785 10k cxa1875ap/am slave address for 4 ch and 4 dh 10k application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 19.2 0.1 + 0.4 9 18 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 3.7 0.1 + 0.4 6.4 0.1 + 0.3 7.62 0.25 0.05 + 0.1 0 ? to 15 ? 16 16pin dip (plastic) 1.0 g sony code eiaj code jedec code dip-16p-01 dip016-p-0300 similar to mo-001-ae 1.all mat surface type. two kinds of package surface: 2.all mirror surface type. package outline unit : mm cxa1875ap cxa1875ap/am 10 cxa1875ap kokubu ass'y package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 19.2 0.1 + 0.4 9 18 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 3.7 0.1 + 0.4 6.4 0.1 + 0.3 7.62 0.25 0.05 + 0.1 0 ? to 15 ? 16 16pin dip (plastic) 1.0 g sony code eiaj code jedec code dip-16p-01 dip016-p-0300 similar to mo-001-ae 1.all mat surface type. two kinds of package surface: 2.all mirror surface type.
11 cxa1875ap/am sony corporation package outline unit : mm purchase of sony s i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. CXA1875AM sct ass'y lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. package structure package material lead treatment lead material package mass sony code eiaj code jedec code sop-16p-l01 sop016-p-0300 copper alloy solder plating epoxy resin 16pin sop (plastic) 9.9 0.1 + 0.4 16 9 18 1.27 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 6.9 1.85 0.15 + 0.4 0.5 0.2 0.2 0.05 + 0.1 0.1 0.05 + 0.2 0.2g 0.15 m 0.24 CXA1875AM package structure package material lead treatment lead material package mass sony code eiaj code jedec code sop-16p-l01 sop016-p-0300 copper alloy solder plating epoxy resin 16pin sop (plastic) 9.9 0.1 + 0.4 16 9 18 1.27 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 6.9 1.85 0.15 + 0.4 0.5 0.2 0.2 0.05 + 0.1 0.1 0.05 + 0.2 0.2g 0.15 m 0.24

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